1. Field of the Invention
The present invention relates generally to semiconductor memory devices and, more particularly, to a semiconductor memory device capable of reducing the time required for a functional testing of an internal circuit.
2. Description of the Background Art
As the capacity of a semiconductor memory device increases, an increase in the test time required for a functional testing of an internal circuit becomes a significant problem. Parallel testing technology for reducing the functional testing time of VLSI memories is proposed in the article by J. Inoue et al, entitled "PARALLEL TESTING TECHNOLOGY FOR VLSI MEMORIES", 1987 ITC Proceedings, pp. 1066-1071. In this parallel testing technology, all memory cells connected to one word line are tested at a time by adopting an on-chip testing circuit system in which a testing circuit for performing a functional testing of a memory and a tested circuit are mounted on a common chip.
FIG. 12 is a schematic block diagram showing the configuration of a memory including an on-chip testing circuit disclosed in the above-described document, which is a circuit for testing provided on the same chip as that of a tested circuit.
Referring to FIG. 12, a memory array 10 includes a plurality of bit line pairs, a plurality of word lines crossing the bit line pairs, and memory cells provided one for each of cross-over points between the bit lines and the word lines.
In this memory, in normal data writing, a data input circuit 101 receives externally applied data D.sub.IN. An externally applied address signal is applied via an address buffer 106 to a column decoder 104 and a row decoder 108. Column decoder 104 decodes the applied address signal to select a bit line connected to memory cells corresponding to the applied address signal. Row decoder 107 decodes the applied address signal, to select a word line connected to memory cells corresponding to the applied address signal. A word driver 108 activates the word line selected by row decoder 107 so as to enable data writing/reading relative to the memory cells connected to the selected word line. Then, the data received by data input circuit 101 is written via a multiplexer 103 into a memory cell provided in correspondence with the cross-over point between the bit line selected by column decoder 104 and the word line activated by word driver 108.
In normal data reading, column decoder 104 and row decoder 107 select a bit line and a word line, respectively, corresponding to an address signal applied through address buffer 106. Word driver 108 activates the word line selected by row decoder 107 similarly to the case of normal data writing. Accordingly, in response to storage data of a memory cell provided corresponding to the cross-over point between the bit line selected by column decoder 104 and the word line selected by row decoder 107, the potential of the selected bit line rises (when the storage data is logical high or an H level) or falls (when the storage data is logical low or an L level).
When no data reading/writing is carried out, two bit lines constituting each bit line pair is equalized at a predetermined potential (in general, V.sub.cc /2, 1/2of a supply potential). In data reading, the potential of the selected bit line rises or falls from the predetermined potential V.sub.cc /2 in response to the storage data of the selected memory cell. A sensing circuit 105 comprises differential amplifier circuits each receiving as inputs the respective potentials of the two bit lines constituting each bit line pair.
More specifically, when the potential of a bit line connected to the selected memory cell rises higher than the potential obtained in equalization, sensing circuit 105 raises the potential of this bit line to a high potential (supply potential) corresponding to a high logic level or the H level and simultaneously lowers the potential of the other bit line paired with this bit line to a low potential (ground potential) corresponding to a low logic level or the L level. Conversely, when the potential of the bit line connected to the selected memory cell falls lower than the potential obtained in equalization, sensing circuit 105 lowers the potential of this bit line to a low potential corresponding to the L level and simultaneously raises the potential of the other bit line paired with this bit line to a high potential corresponding to the H level. As a result, complementary data associated with the storage data of the selected memory cell is read onto the selected bit line and the other bit line paired therewith.
In normal data reading, as the result that sensing circuit 105 performs the foregoing operation, a potential appearing on the bit line connected to the selected memory cell, (which is the bit line selected by column decoder 104) is transmitted as the storage data of the selected memory cell via multiplexer 103 to a data output circuit 102. Data output circuit 102 outputs the data from multiplexer 103 as final read data D.sub.OUT.
A determination is made as to the presence/absence of defects of memory cells in the memory array, for example, dependently upon whether or nor data written in advance in the memory cells is the same data read from these memory cells. In this case, in order to test all the memory cells in the memory cell array, data should be read from each memory cell after the data is written in advance in all the memory cells. In normal data writing, however, data can be written into only one memory cell at one time. Thus, if the total number of memory cells in the memory array increases due to an increase in the storage capacity of the memory, a long time has to be spent for data writing for testing, resulting in an increase in the time required for a functional testing of the memory, in which the above-described presence/absence of defects of the memory cells and other problems are checked.
Thus, in the memory shown in FIG. 12, a testing circuit 20, including a write circuit 30 for performing data writing for testing in a different path from that established in normal data writing, is provided on a common chip on which memory array 10, data input circuit 101, data output circuit 102, multiplexer 103, column decoder 104, sensing circuit 105, address buffer 106, row decoder 107 and word driver 108 are provided, in order to reduce the time required for data writing for testing.
Testing circuit 20 includes write circuit 30, a comparison circuit 40 and a detection circuit 50. In testing, write circuit 30 receives as an input, data D.sub.TE for testing which is to be written in advance. Write circuit 30 simultaneously writes the data D.sub.TE into all memory cells connected to a single word line at a time. When this writing is completed, comparison circuit 40 is supplied with inversion data D.sub.TE of the previously written data D.sub.TE as expected data. Also, the operation of row decoder 107 as described above causes data to be read simultaneously from all the memory cells connected to the single word line, into which the data D.sub.TE is written in advance. Comparison circuit 40 makes a comparison between the read data and the inversion data D.sub.TE .
As the result of comparison by comparison circuit 40, if none of the read data match the inversion data D.sub.TE , i.e., the same data as the previously written data are read from all of the memory cells connected to the single word line, then detection circuit 50 outputs a flag signal DS of a predetermined logic level indicating that no defective memory cells exist. Conversely, if any of the read data matches the inverted data D.sub.TE , i.e., different data from the previously written data is read from at least one of the memory cells connected to the single word line, then detection circuit 50 outputs a flag signal DS of the opposite logic level to the predetermined logic level, indicating that a defective memory cell exists.
As described above, in this memory, a so-called line test is carried out by testing circuit 20, in which the presence/absence of defects of all the memory cells arranged in one word line direction (a row direction) in memory array 10 is checked at a time.
FIG. 13 is a circuit diagram showing the configuration of testing circuit 20 and peripheries thereof. The circuit of FIG. 13 is described in "1987 International TEST Conference", pp. 1066-1071. Referring to FIG. 13, memory array 10 is connected with testing circuit 20. Four word lines WL1-WL4 and two bit line pairs B1, B1 and B2, B2 are representatively shown.
Write circuit 30 includes N channel MOS transistors Q1-Q4, a write control line WC and write lines W and W. Comparison circuit 40 includes comparators having a common structure and provided corresponding to respective bit line pairs. The comparators provided corresponding to bit line pairs B1, B1 and B2, B2 are representatively shown in FIG. 13. A comparator CP1 corresponding to bit line pair B1, B1 includes N channel MOS transistors Q5 and Q6. Similarly, a comparator CP2 corresponding to bit line pair B2, B2 includes N channel MOS transistors Q7 and Q8.
A description will now be made of operation of testing circuit 20 upon line testing.
Data of the H level and that of the L level, for example, are first supplied to write lines W and W, respectively, so that the potential of write control line WC is raised to the H level. Accordingly, transistors Q1-Q4 are rendered conductive, so that the potential of bit lines B1 and B2 attains the H level, and the potential of bit lines B1 and B2 attains the L level. Now, the potential of word line WL1, for example, is raised to the H level by word driver 108 in FIG. 12 so that the word line may be activated. In response to the rise of the potential of word line WL1, data of the H level is written into memory cells M1 and M3. After this writing, the potential of word line WL1 attains the L level by word driver 108 so that the word line may be deactivated, and also the potential of write control line WC attains the L level.
Thereafter, when the potential of word line WL1 is again raised to the H level by word driver 108, potential changes depending on the data stored in memory cells M1 and M3 occur on bit lines B1 and B2. The potential changes on bit line pair B1, B2 are amplified by sensing circuit 105 in FIG. 12, as described above. As a result, each of bit line pairs B1, B1 and B2, B2 attains complementary potentials depending on data read from memory cells M1 and M3.
Data of the L level and that of the H level are then supplied to write lines W and W, respectively, oppositely to the case of data writing.
Detection circuit 50 includes an inverter G1, an N channel MOS transistor Q9 connected between an input terminal of inverter G1 and ground and having its gate receiving the potential on the connecting point between transistors Q5 and Q6 (an output terminal of comparator CP1), an N channel MOS transistor Q10 having its gate receiving the potential on the connecting point between transistors Q7 and Q8 (an output terminal of a comparator CP2), and a precharge circuit 51 connected to a connecting line N11 connecting transistors Q9 and Q10 and inverter G1. In practice, not only transistors Q9 and Q10 but also N channel MOS transistors are provided between inverter G1 and ground, one for each comparator provided corresponding to each of all the other bit line pairs. Precharge circuit 51 precharges connecting line N11 to the H level upon the start of testing.
When data is read out of memory cells M1 and M3, into which data for testing is written as described above, the potential of bit lines B1 and B2 attains the H level, and the potential of bit lines B1 and B2 attains the L level when the read data is at the same H level as that of the previously written data for testing. Accordingly, transistors Q5 and Q7 are rendered conductive in comparators CP1 and CP2, so that the potential of a connecting line N9 connecting comparator CP1 and transistor Q9 and that of a connecting line N10 connecting comparator CP2 and transistor Q10 both attain the L level in response to the potential on write line W. Thus, transistors Q9 and Q10 are put in an OFF state, so that the potential of connecting line N11 precharged by precharge circuit 51 does not fall. Accordingly, if data read from any other memory cells connected to word line WL1 is at the same H level as that of the previously written data, none of the N channel MOS transistors provided one for each comparator in detection circuit 50 are rendered conductive, so that a signal of the L level representing that no defective memory cells exist is output from inverter G1. This output of inverter G1 is the above-described flag signal DS.
Assuming now that memory cell M1 is defective, for example, data read from memory cells M1 and M3 attain the L level and the H level respectively despite the fact that data of the H level is written in memory cells M1 and M3. In response to the data attaining the L level and the H level, sensing circuit 105 performs the opposite operation from that of the foregoing case, so that the potentials of bit lines Bl and Bl attain the L level and the H level, respectively. Write lines W and W are supplied with data of the L level and that of the H level, respectively. Accordingly, transistor Q6 becomes conductive in response to the H level potential on bit line Bl, and connecting line N9 is charged to the H level. This causes transistor Q9 to be conductive, so that connecting line N11 is coupled to ground to be discharged to the L level. As a result, a flag signal DS of the H level representing that defective memory cells exist is output from inverter G1. More specifically, if there is one defective memory cell of all memory cells connected to a selected word line, then an output of a comparison circuit provided corresponding to a bit line pair corresponding to the defective memory cell causes a corresponding transistor in detection circuit 50 to be conductive, so as to lower the potential of connecting line N11 to the L level. This causes flag signal DS to attain the H level.
In this manner, the same data is written via write lines W and W in the memory cells of a single row connected to the selected single word line. Then, data is read from the memory cells of that row, and the opposite data from the previously applied data are applied to write lines W and W, respectively. When all the data read from the memory cells of the single row match the data previously written in those memory cells of the single row, the flag signal DS attains a logic level indicating that no defective memory cells exist. On the other hand, if there is at least one defective memory cell of the memory cells of the single row connected to the single word line, and data read from that defective memory cell does not match previously written data, the flag signal DS attains a logic level indicating that the defective memory cell exists.
As described above, in the memory including the on-chip testing circuit shown in FIG. 13, after the data for testing is written in all the memory cells connected to the single word line at the same time, a test is carried out for the memory cells at the same time. Therefore, a substantial reduction in test time is expected.
As has been mentioned above, in the conventional semiconductor memory device enabling the reduction in the test time, since the write control line and the write lines are provided in common to all the bit lines as shown in FIG. 13, identical data is written into the memory cells of a single row connected to a single word line. In other words, the pattern of test data entered in the memory cells of the single row is all the H level data or the L level data. Thus, it is impossible to perform a test which is enabled by writing of alternate data into two adjacent memory cells in a row direction, e.g., a detection of data interference between the adjacent memory cells, and the like. Therefore, in the conventional art, although the test time can be decreased by line testing, the kinds of tests practicable in shorter test time are limited. It is thus becomes difficult to detect defective memory cells from many aspects, resulting in a degradation in sensitivity of detection of the defective memory cells.